The Athena/Aether implementation uses the following hardware:
Details here
Using the new DFC (Direct Fourier Conversion) protocol for input of ADC samples, it processes those samples with a CUDA capable GPU. It then forwards the resultant IQ data via the new openHPSDR protocol to a second program that distributes them to one or more dsp servers. These servers send PCM16 data directly to a modified version of of fldigi: flRadio. Control of frequency, band, etc. is provided by flControl.
The ADC samples are currently provided by a modified FPGA program running on an Anan 200D. Sampling at a rate of 61.44MHz the GBit ethernet is saturated with 983.04 Mbps of data. This is a short term solution until the Minerva becomes available. Minerva will use the PCIe bus, and will be able to provide samples at the full 122.88MHz rate.
Note that the dfcSDR suite only supports receive at this point. FPGA firmware to allow for communication with the transmit section of the Anan is under development.
The organization of the programs is modelled on ghpsdr3-alex, and is to some degree compatible with it:
Athena/Aether & friends are all currently running on Ubuntu, both 14.04LTS and 16.04LTS. It should be a fairly easy port to any Unix/Posix system that can run the Nvidia CUDA driver/toolkit.
A source of raw ADC samples is required. I currently use a modified Anan-200D. Be aware that this modification requires loading of custom FPGA firmware, and that it renders the Anan-200D usable only as a receiver. Minerva will soon be available to solve this limitation. It is a PCIe card that will both transmit/receive, and has the bandwidth necessary for full ADC sample rate.
Others are working on FPGA firmware that will allow the Anan-100D/Anan-200D (and possible lesser Anans) to use the new openHPSDR Protocol. Note that these will use the new protocol, but will NOT be examples of DFC systems. The important distinction is that a DFC system does the processing of ADC samples on a general purpose CPU, while a traditional system such as an Anan does the processing in an onboard FPGA.
The chief advantage of the DFC model is that new code (FFT algirithms, etc.) can be quickly coded/compiled/tested, while the traditional FPGA model can take hours (if not a day or more) to run the same cycle.
Other programs compatible with Athena:
As an alternative to a desktop/PCIe CUDA card, others are using: